1. Field of the Invention
The present invention is directed to a method and system for removing ion implanted photoresist, and more particularly to a method and system for effectively stripping a photoresist layer damaged by high dose ion implantation.
2. Discussion of the Background
Photoresist has been used in the fabrication of very large-scale integrated (VLSI) circuits for years. It works as a masking material for shielding ion implantation in selected areas, and transferring patterns into various layers (e.g., oxide, nitride, polysilicon and metals). After ion implantation or pattern transfer is carried out, the photoresist layer needs to be removed completely. Generally, the removal of photoresist, also called stripping or ashing, is performed in a plasma containing (high amounts of) oxygen. The oxygen atoms react with the C (carbon) and H (hydrogen) in the photoresist, forming volatile products that are then exhausted from the system. The requirements of a photoresist stripping process are summarized as: 1) completeness, 2) or minimal or no charge damage, 3) minimal or no contamination, and 4) high throughput. As the device feature size shrinks, those requirements are becoming increasingly stringent.
While non-ion-implanted photoresist can be stripped fairly easily in an oxygenated plasma, it is difficult to completely strip resist that has been damaged by high dose ion implantation by plasma dry etching. During high dose ion implantation, the surface layer of the photoresist is severely damaged or carbonized such that a crust is formed which is difficult to remove. In the case of some plasma dry etching applications, polymers or other materials generated in the process can deposit onto the sidewalls of the photoresist pattern or etched features and form xe2x80x9cveilsxe2x80x9d along the pattern edges that generally require both dry stripping and wet processing to remove. When a conventional oxygen-only process is used, those crust layers or xe2x80x9cveilsxe2x80x9d will be left on the wafer surface as residues after ashing.
As an additional concern, there are many charged particles (ions and electrons) in the plasma discharge. A wafer in the plasma will draw electrons or ions, depending on the RF cycle applied to the plasma and the bias applied to the wafer itself, onto its surface. As electrons have much lower mass and travel at much higher speed, a negative potential will normally be developed on the wafer as a result of surface electron accumulation. If this negative potential is not balanced across the wafer, the resulting potential difference may cause potential differences across the wafer surface and across the thin oxide layers that may exist between the surface conducting layers and the semiconductor substrate. When the potential difference is high enough, it may cause damage, such as charge traps or even dielectric breakdown, in the thin oxide layer. Furthermore, UV radiation generated in the plasma may also create charge traps in oxide layers. As photoresist stripping is used in many steps of the VLSI fabrication process, minimal or no charge or UV damage is allowed, in order to preserve the yield of manufactured devices.
Metallic contents, although minimal, are found in most of the commercial photoresists and developers. Since those metallic contents cannot be removed by oxygen plasma, they will stay on the substrate surface as xe2x80x9cresiduesxe2x80x9d at the endpoint of the resist stripping. Overetching, which is commonly required to completely remove the photoresist over the entire wafer, can drive those metallic contents into the films that are present on the wafer surface and result in metallic contamination. Similar phenomena can happen to those ion implanted impurities (e.g., phosphorous and arsenic) as those impurities are oxidized in the oxygen plasma and driven into the surface layers during overetching.
High throughput, one of the critical specifications for any commercial equipment, requires the stripping process to be as short as possible. Besides a reliable, fast and efficient wafer transfer system and pumping system, the resist stripping rate needs to be very high, e.g.,  greater than 4 mm/min, to achieve high throughput.
Many apparatuses and processes have been developed for removing photoresist from semiconductor wafer surfaces using oxygen plasma discharge. In the conventional method, wafers with resist coatings are simply placed directly in the oxygen plasma generated in a barrel asher. While the throughput of the batch processing in barrel asher is high, charge damage and contamination can result since the ions are in direct contact with the wafers and long overetching times are used.
U.S. Pat. No. 5,478,403 (Shinagawa et al., 1995) introduces an apparatus for resist ashing applications. The apparatus uses a microwave source to generate the oxygen-containing plasma. As shown in FIG. 1, the microwave-generated plasma is introduced to a downstream process chamber, through a plasma-transmitting plate, to where the resist coated wafer is to be treated. While the microwave is efficient in generating oxygen radicals, the ions in the plasma may have high ion energy and cause charge damage and contamination if in direct contact with the wafer surface. Those ions must be eliminated from the flux on their way from the plasma source to the wafer substrate. The transmitting plate captures charged particles in the plasma while allowing the transmission of neutral active species to thereby ash the photoresist coating without accumulating charges on the wafer surface. The wafer is placed on a chuck that is capable of adjusting its position to vary the distance between the wafer and the plasma transmitting plate.
Similar concepts of using microwave-generated plasma in resist stripping can be found in U.S. Pat. No. 5,562,775 (Mihara et al., 1996), U.S. Pat. No. 5,780,395 (Sydansk et al., 1998). U.S. Pat. No. 5,773,201 (Fujimura et al., 1998), and U.S. Pat. No. 5,545,289 (Chen et al., 1996). As described therein, the wafers to be processed are placed downstream from the plasma source chamber. The ions generated by the microwave source recombine on the way to the wafer so that only neutral radicals reach the wafer and affect the ashing process.
In the case of not using a downstream approach the wafer is placed close to the source plasma, and a charge trapping plate or grid is generally used in order to minimize charge damage. The use of a transmitting plate to eliminate the charged particles from reaching the wafer surface is discussed in U.S. Pat. No. 4,859,303 (Kainitsky et al., 1989) and xe2x80x9cAdvanced photoresist strip with a high pressure ICP sourcexe2x80x9d (Savas et al., Solid State Technology, October 1996, pp. 123-128) (hereinafter xe2x80x9cSavasxe2x80x9d).
The problem of stripping high-dose ion-implanted photoresist, when the above mentioned microwave source and charge-trapping plate are used, is that the oxygen radicals arriving at the wafer surface are not very effective in removing the carbonized crusted skin of the resist coating. During the stripping process, the skin layer tends to crack due to stress and softening of the underlying uncarbonized resist, and the oxygen radicals penetrating through those cracks can react with the underlying xe2x80x9csoftxe2x80x9d resist at a very high rate. The volatile products generated from ashing the underlying xe2x80x9csoftxe2x80x9d resist layer will cause the hardened skin layer to crack even further and eventually break into many small pieces. This is generally referred to as xe2x80x9cresist popping.xe2x80x9d Those small pieces of hardened resist skin will stick on the substrate surface and become very difficult to be removed completely by oxygen radicals, even with long overetching time.
U.S. Pat. No. 4,861,424 (Fujimura et al., 1989) (hereinafter xe2x80x9cthe ""424 patentxe2x80x9d) describes a two-step process designed specifically for stripping ion-implanted photoresist. It uses a plasma containing a mixture of hydrogen and nitrogen in the first processing step and oxygen plasma (or a wet chemical treatment) in the second processing step. In the first step, the hydrogen radicals generated in the plasma react with the carbon in the carbonized resist and the implanted ions (e.g., P, As or B) breaking the bonds joining them. The resulting hydride compounds are volatile, even at room temperature. The fact that the reaction products are volatile at low temperature is particularly important for leaving almost no residue on the substrate since a temperature higher than the softening temperature of un-hardened resist material (about 120xc2x0-150xc2x0 C.) may cause resist popping.
In the ""424 patent, the first step is performed in a parallel plate RIE (reactive ion etching) mode reactor and second step in a microwave downstream asher, as shown in FIG. 2. The problem with this approach is that a parallel plate RIE mode reactor has a high electron temperature and high ion energies which may cause charge and lattice damage as well as contamination to the substrate.
U.S. Pat. No. 5,773,201, (Fujimura et al.) describes a process that adds water vapor into oxygen to create the ashing gases. The addition of water vapor lowers the activation energy of the ashing reaction and increases the reaction species, thus increasing the ashing rate and decreasing the process temperature. However, the ashing rate in the disclosure is only about 3000 xc3x85/min.
Savas describes a resist stripping system that utilizes an inductively coupled plasma source with a Faraday shield to reduce RF capacitive coupling to the plasma. The nearly pure inductive coupling nature reduces the plasma potential. The use of high pressure (xcx9c1 Torr) and low RF power level (xcx9c1 W/cc) produces a plasma with high dissociation and low ionization. Thus this source provides high resist stripping rate but very low charge damage. However, as the ashing of photoresist is purely by chemical reaction, for the ashing rate to be high, the wafer temperature is kept high (e.g., between 200xc2x0 C.-250xc2x0 C.). Thus, the system has a potential resist popping problem when used for stripping ion implanted photoresist because of the high wafer temperature. On the other hand, if a low processing temperature is used to prevent resist popping, the ashing rate is compromised, resulting in lower throughput.
In summary, various systems have been developed for stripping photoresist in semiconductor device fabrication. While they are effective in stripping normal resist, most of them have problems when used for stripping ion implanted resist, where a carbonized surface layer is created. Although different apparatuses and processes have been developed to deal with the problem, they suffer from either introducing potential charge and lattice damage in the case of RIE mode asher, or lower throughput in the case of low temperature processing.
Accordingly, it is an object of the present invention to provide an improved method of stripping ion implanted photoresist.
This and other advantages are made possible by a two step process in which the carbonized surface layer and the underlying soft resist are stripped in two separate steps using different processes in an Electrostatically Shielded RF (ESRF) plasma reactor. The first stripping step uses a combination of radical and controllable low energy ion-assisted etching of the carbonized layer using low processing temperature. The second stripping step uses high concentration oxygen radical ashing to strip the soft resist at a high processing temperature. The ESRF source is able to produce a plasma with adjustable dissociation and ionization rates. When operating at relatively high pressure (e.g., 1 Torr) and low power (e.g., 1 W/cc), it produces high dissociation rate and low ionization rate. The ionization rate increases as the power increases and the pressure decreases.
The combination of the above features makes it possible to strip ion-implanted resist. As most of the RF is coupled into the plasma inductively through the slots in a metallic electrostatic shield (hereinafter xe2x80x9cE-shieldxe2x80x9d), the plasma density decays rapidly below the lower extent of the slots at high pressure. The nature of the pure inductive coupling, when the electrostatic shield is grounded, results in very low plasma potential and very low ion energy. This enables the plasma to be confined to where it is generated. Measurements show that the ion density at a location 25 mm below the source is less than 1xc3x97108/cm3. That means the wafer can be placed very close to the plasma source without causing charge damage. As oxygen radical concentration decays with distance from the plasma source, the closer the wafer is placed to the plasma, the higher the concentration of oxygen radicals arriving at the wafer surface, thus the higher the stripping rate. Another advantage of placing the wafer closer to the plasma source is, when necessary, a small amount of ions can be drawn to the wafer surface to assist the removal of the hardened skin layer.
With the use of a bias shield, the degree of capacitive coupling of the RF power to the plasma, and thus the plasma potential, can be adjusted. When the plasma potential is raised higher, the ion bombardment of the chamber wall and the wafer substrate increases. When the bias level is high, the plasma potential becomes high and ion bombardment to the chamber wall increases. This can be used as a method to clean the chamber inside surface periodically without opening the chamber, resulting in prolonged time between chamber wet clean and higher overall system uptime.
When the bias shield bias level is low, the plasma potential is increased slightly and a small amount of ions, along with radicals, can be introduced to the wafer surface. This phenomenon can be utilized in the first processing step to assist in the removal of the hardened skin layer.